Pixel unit and imaging device

ABSTRACT

An pixel unit includes a photoelectric conversion element, a transfer transistor having a transfer gate abutting on the photoelectric conversion element, and a floating diffusion region on which the transfer gate abuts, wherein the transfer gate includes a first gate portion having a first gate width in a gate width direction, the first gate portion abutting on the floating diffusion region and extending away from the floating diffusion region in a gate length direction, and a second gate portion having a second gate width narrower than the first gate width in the gate width direction, the second gate portion extending continuously from the first gate portion in the gate length direction, and wherein a width of the second gate portion gradually decreases from the first gate width to the second gate width toward a direction away from the first gate portion.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional of U.S. application Ser. No. 15/437,850filed on Feb. 21, 2017, the entire contents of which are herebyincorporated by reference. The present application is also based on andclaims priority to Japanese patent application No. 2016-043816, filed onMar. 7, 2016, the entire contents of which are hereby incorporated byreference.

BACKGROUND OF THE INVENTION 1. Field of the Invention

The disclosures herein relate to a pixel unit and an imaging device.

2. Description of the Related Art

Solid-state imaging devices such as CMOS (i.e., complementarymetal-oxide semiconductor) imaging sensors are manufactured by use of atypical semiconductor manufacturing process. A single chip may beconfigured to have both an analog circuit and a digital circuitimplemented therein. Significant advantages such as reduction of thenumber of peripheral ICs may thus be achievable.

A solid-state imaging device includes a pixel unit having a plurality ofarranged pixels and peripheral circuits disposed in the surrounding areaof the pixel unit. Each pixel includes a photoelectric conversionelement (PD) such as a photodiode, pixel transistors of various types,and a floating diffusion (FD) region for converting electric chargeobtained through photoelectric conversion into voltage. A transfertransistor (TX) included in the pixel transistors has a transfer gate(TG) for transferring electric charge from the PD region to the FDregion for read-out.

Some related-art solid-state imaging devices have a structurecharacterized by an extended part which is formed by extending a portionof the gate of a transfer transistor from the main part of the gatetoward the PD region.

SUMMARY OF THE INVENTION

In one embodiment, an pixel unit includes a photoelectric conversionelement, a transfer transistor having a transfer gate abutting on thephotoelectric conversion element, and a floating diffusion region onwhich the transfer gate abuts, wherein the transfer gate includes afirst gate portion having a first gate width in a gate width direction,the first gate portion abutting on the floating diffusion region andextending away from the floating diffusion region in a gate lengthdirection, and a second gate portion having a second gate width narrowerthan the first gate width in the gate width direction, the second gateportion extending continuously from the first gate portion in the gatelength direction, and wherein a width of the second gate portiongradually decreases from the first gate width to the second gate widthtoward a direction away from the first gate portion.

BRIEF DESCRIPTION OF THE DRAWINGS

Other objects and further features of embodiments will be apparent fromthe following detailed description when read in conjunction with theaccompanying drawings.

FIG. 1 is a drawing illustrating an example of a pixel unit according toa first embodiment;

FIG. 2 is a drawing illustrating the electric field of the example ofthe pixel unit;

FIG. 3 is a drawing illustrating an example of a pixel unit according toa second embodiment;

FIG. 4 is a drawing illustrating an example of a pixel unit according toa third embodiment;

FIG. 5 is a drawing illustrating an example of a pixel unit according toa fourth embodiment;

FIG. 6 is a drawing illustrating an example of a pixel unit according toa fifth embodiment;

FIG. 7 is a drawing illustrating an example of a pixel unit according toa sixth embodiment;

FIG. 8 is a drawing illustrating an example of part of an imaging devicehaving pixel units illustrated in FIG. 6;

FIG. 9 is a schematic block diagram illustrating an example of theimaging device;

FIG. 10 is a drawing illustrating the circuit configuration of a pixelused in the pixel unit of the imaging device illustrated in FIG. 9;

FIG. 11 is a drawing illustrating the operation timing of the pixel unitof the imaging device illustrated in FIG. 9; and

FIG. 12 is a drawing illustrating an example of a camera system in whichthe imaging device has the pixel unit.

DESCRIPTION OF THE PREFERRED EMBODIMENTS <Problems to be Solved byEmbodiments>

A related-art imaging device has an extended part relative to the mainpart of a transfer gate, and the existence of such an extended part endsup reducing the area size of the PD region. This configuration causesthe number of saturated electrons in the PD region to decrease, whichresults in insufficient amount of light input. Further, the existence ofa portion having a different gate size (gate length in particular) inthe transfer gate causes the distance (i.e., the gate length of thetransfer transistor TX) from the PD region to the FD region to beuneven, thereby generating variation in the electric potential of the FDregion at points (proximity points) close to the transfer transistor TX.

With such variation in electric potential, a lengthy time is requiredfor electric charge to move from a point in the PD region at a distancefrom the transfer transistor TX to a point abutting on the transfertransistor TX. As a result, degradation of the transfer characteristicsmay occur. In this manner, the structure of the related-art solid-stateimaging device may cause a detrimental effect on the transfercharacteristics. There may thus be a need for an imaging device that hasimproved transfer characteristics while securing sufficient light input.

Embodiments

In the following, embodiments will be described by referring to theaccompanying drawings. In these drawings, the same or correspondingelements are referred to by the same or corresponding numerals, and adescription thereof will be omitted. FIG. 1 is a drawing illustratingthe structure of a pixel that is an example (i.e., first embodiment) ofa pixel unit. A pixel 1 includes a photodiode 3, a transistor 5, and adiffusion region 7.

The photodiode 3, which is electrically coupled to the transistor 5, hasthe function to convert incident light into electric charge. Althoughnot illustrated, the photodiode 3 is configured as a pinnedphotoelectric conversion element such that an n-type semiconductorregion (n+) serving as an electric charge accumulation region is formedin a p-type semiconductor well, with a p-type semiconductor region (p+)formed on the n-type semiconductor region.

The photodiode 3 is an example of a photoelectric conversion elementincluded in the pixel unit.

The transistor 5, which is electrically coupled to the photodiode 3, hasa gate 51 abutting on the photodiode 3. The transistor 5 is coupled tothe photodiode 3 via a channel under the gate 51. The transistor 5 hasthe function to transfer electric charge converted by the photodiode 3to the diffusion region 7.

The transistor 5 is an example of a transfer transistor included in thepixel unit. Further, the gate 51 of the transistor 5 is an example of atransfer gate constituting the transfer transistor.

The diffusion region 7 abuts on the gate 51 of the transistor 5 suchthat the transistor 5 is placed between the photodiode 3 and thediffusion region 7, and is electrically coupled to the transistor 5. Theplan shape of the diffusion region is a quadrilateral such as arectangle, a square, or the like. The diffusion region 7 containsdiffused impurities to form a n-type semiconductor region (n+). Thediffusion region 7 corresponds to the drain of the transistor 5, whichaccumulates electric charge transferred through the transistor 5.

The photodiode 7 is an example of a floating diffusion region includedin the pixel unit.

The pixel unit of FIG. 1 further includes a device isolation region 9surrounding the photodiode 3, the transistor 5, and the diffusion region7. The device isolation region 9, which is formed as a p-typesemiconductor region (p+ region), may have a portion extending in thechannel area of the gate 51 of the transistor 5 (i.e., extending underthe gate 51 of the transistor 5).

The provision of the device isolation region 9 serves to electricallyisolate the photodiode 3, the transistor 5, and the diffusion region 7of the pixel 1 from another pixel 1.

Further, the gate 51 of the transistor 5 includes a first gate portion52 and a second gate portion 53 that have different gate widths. Thefirst gate portion 52, which has a first gate width GW1 in the gatewidth direction WD, abuts on the diffusion region 7 and extends awayfrom the diffusion region 7 in the gate length direction LD.

The gate length direction LD refers to the direction in which carriersmove in the channel when the transistor 5 operates, and lies in thevertical direction of FIG. 1. The gate width direction WD refers to thedirection perpendicular to the gate length direction LD, and lines inthe horizontal direction of FIG. 1. Namely, the direction in which thefirst gate portion 52 extends (i.e., the gate length direction LD inwhich the first gate portion extends away from the diffusion region 7)refers to the downward vertical direction of FIG. 1.

The second gate portion 53, which has a second gate width GW2 narrowerthan the first gate width GW1 in the gate width direction WD, extendscontinuously from the first gate portion 52 in the gate length directionLD. The second gate portion 53 extending continuously from the firstgate portion 52 may be formed seamlessly with the first gate portion 52as part of a unitary, continuous piece, or may be formed as a distinctmember separate from the first gate portion 52.

The width of the second gate portion 53 gradually decreases from thefirst gate width GW1 to the second gate width GW2 toward the directionaway from the first gate portion 52. The direction away from the firstgate portion 52 is the downward vertical direction of FIG. 1 similarlyto the direction in which the first gate portion 52 extends (i.e., thegate length direction LD in which the first gate portion 52 extends awayfrom the diffusion region 7).

Namely, the gate width of the gate 51 is constant in the first gateportion 52 (i.e., equal to the first gate width GW1), and graduallydecreases in the second gate portion 53 toward the tip (i.e., side 51 f)of the second gate portion 53 from a vicinity 53 a of the first gateportion 52.

In other words, the gate width of the second gate portion 53 decreasesfrom the first gate width GW1 to the second gate width GW2 toward thetip (i.e., side 51 f) of the second gate portion 53 as the second gateportion 53 extends from the vicinity 53 a of the first gate portion 52.

The gate 51 in FIG. 1 is situated between the photodiode 3 and thediffusion region 7. The diffusion region 7, which has a width narrowerthan the first gate width GW1, abuts on an end 51 a of the gate 51(i.e., the first gate portion 52) through this narrower width.

The gate 51 in FIG. 1 is situated between the photodiode 3 and thediffusion region 7. The diffusion region 7, which has a width narrowerthan the first gate width GW1, abuts on an edge 51 a of the gate 51(i.e., the first gate portion 52) through this narrower width.

The arrangement in which the photodiode 3 surrounds the gate 51 of thetransistor 5 having such a shape, except for the edge 51 a abutting onthe diffusion region 7, allows the photodiode 3 to have a large areasize without the need to increase the entire size of the pixel 1. Withthis arrangement, a sufficient amount of light input into the photodiode3 is secured, and so is a sufficient number of saturated electrons,despite the provision of the gate 51 of the transistor 5.

Moreover, the above-described shape of the gate 51 of the transistor 5serves to ensure that the distance from the photodiode 3 to thediffusion region 7 is almost constant regardless of the position. As aresult, electric potential within the area of the photodiode 3 is madepositive from a distant area 3 a away from the transistor 5 to avicinity area 3 b next to the transfer transistor.

Consequently, the transfer electric field within the area of thephotodiode 3 is improved between the distant area 3 a away from thetransistor and the vicinity area 3 b next to the transfer transistor(i.e., without the occurrence of a reverse electric field). The transfercharacteristics of the imaging device is thus improved.

The gate 51 of the transistor 5 preferably has a taper shape in thesecond gate portion 53 as illustrated in FIG. 1. The provision of such atapering gate 51 between the photodiode 3 and the diffusion region 7serves to provide a substantially constant distance between thephotodiode 3 and the diffusion region 7.

Consequently, the provision of the tapering gate 51 serves to keep apositive electric potential from the photodiode 3 to the gate 51 of thetransistor 5 (i.e., from the distant area 3 a to the vicinity area 3 bin the photodiode 3). Since this arrangement enables the improvement ofa transfer electric field in the area of the photodiode 3, the provisionof the tapering gate 51 serves to improve the transfer characteristicsof the imaging device.

The plan shape of the gate 51 is preferably formed by cutting off two ofthe four corners of a rectangle on the far side thereof from thediffusion region 7 as illustrated in FIG. 1. Specifically, the planshape of the gate 51 is constituted by six sides and six vertices asillustrated in FIG. 1. The side that faces toward the diffusion region 7among the six sides corresponds to the edge 51 a of the gate 51 (i.e.,the first gate portion 52) that abuts on the diffusion region 7.

Two of the remaining five sides are sides 51 b and 51 c that are part ofthe first gate portion 52. The sides 51 b and 51 c each meeting the side51 a are situated opposite to each other in the width direction WD. Theremaining three sides are sides 51 d, 51 e, and 51 f that are part ofthe second gate portion 53. The sides 51 d and 51 e of these three sidesmeet the sides 51 b and 51 c, respectively, and are situated opposite toeach other in the gate width direction WD while extending at an anglerelative to the gate length direction LD.

The side 51 f, which meets both the sides 51 d and 51 e, is situatedopposite to the side 51 a in the gate length direction LD. These threesides (i.e., sides 51 d, 51 e, and 51 f) together form the shape of thesecond gate portion 53 whose width gradually decreases from the firstgate width GW1 to the second gate width GW2. In other words, these threesides (i.e., sides 51 d, 51 e, and 51 f) together form the taperedsecond gate portion 53.

In FIG. 1, the gate 51 is placed between the photodiode 3 and thediffusion region 7 such that the five sides thereof (i.e., sides 51 bthrough 51 f), except for the side 51 a, abut on the photodiode 3.Namely, the photodiode 3 surrounds the gate 51 on the five sides (i.e.,sides 51 b through 51 f) thereof, except for the side 51 a.

The provision of the tapering gate 51 having such a shape between thephotodiode 3 and the diffusion region 7 serves to provide asubstantially constant distance between the photodiode 3 and thediffusion region 7 with high precision.

Accordingly, electric potential is consistently kept at a positive levelfrom the photodiode 3 to the gate 51 of the transistor 5 (i.e., from thedistant area 3 a to the vicinity area 3 b in the photodiode 3). Sincethis arrangement enables the consistent improvement of a transferelectric field in the area of the photodiode 3, the provision of such agate 51 reliably improves the transfer characteristics of the imagingdevice.

In the example illustrated in FIG. 1, the plan shape of the gate 51 is ahexagon, all the six sides of which are straight line segments. However,the six sides of the gate 51 are not limited to straight line segments.For example, the two sides (i.e., sides 51 d and 51 e) that are part ofthe tapered second gate portion 53 among the six sides, or one of thesetwo, may be a curved line segment.

Moreover, the photodiode 3, the gate 51 of the transistor 5, and thediffusion region 7 are preferably aligned in line. This arrangementserves to provide a constant distance from the photodiode 3 to thediffusion region 7 through the gate 51 of the transistor 5 with yethigher precision.

FIG. 2 is a drawing illustrating the state of an electric field of thephotoelectric conversion element in the example of the pixel unitconstituting the imaging device. FIG. 2 illustrates an electricpotential observed at the time of transferring electric charge from thephotoelectric conversion element disposed in the pixel unit.

As can be seen in FIG. 2, electric potential is distributed such thatthe maximum electric potential extends from the vicinity area 3 b of thephotodiode 3 situated in the vicinity of the transistor 5 to the distantarea 3 a of the photodiode 3 situated away from the transistor 5.

As viewed from a different angle, the electric filed is consistentlypositive from the distant area 3 a to the vicinity area 3 b in the areaof the photodiode 3. It follows that there is no reverse electric fieldfrom the distant area 3 a to the vicinity area 3 b in the area of thephotodiode 3. In this manner, FIG. 2 shows that there is an improvementin transfer characteristics as a result of the provision of the gate 51that makes insufficient transfer unlikely to happen. Here, the term“insufficient transfer” refers to the situation in which some electriccharge is left unused in the area of the photodiode 3.

FIG. 3 is a drawing illustrating an example of the pixel unitconstituting an imaging device according to a second embodiment. In thepixel 1 of FIG. 3, the diffusion region 7 includes two regions havingrespective, different diffused impurity concentrations. The regionhaving higher impurity concentration is a high concentration region 7 a,and the region having lower impurity concentration is low concentrationregions 7 b.

The impurity concentration of the high concentration region 7 a may be1×10¹⁹ cm⁻³ or higher. The impurity concentration of the lowconcentration regions 7 b may be lower than 1×10¹⁹ cm⁻³.

The high concentration region 7 a is a high-impurity-concentrationregion (N+), and is in contact with the bottom of the gate 51 of thetransistor 5. The low concentration regions 7 b, which are situated nextto the high concentration region (N+), are in contact with the gate 51of the transistor 5. The low concentration regions 7 b are regions (N−)having lower impurity concentration than the high concentration region(N+).

The high concentration region 7 a is an example of a first diffusionregion among the diffusion regions of the pixel unit constituting theimaging device. The low concentration regions 7 b are an example ofsecond diffusion regions among the diffusion regions.

The provision of the high concentration region and the low concentrationregions allows the electric charge transferred through the transistor 5to move easily to the low concentration regions having a shallowpotential. The electric potential moved to the low concentration regionshaving a shallow potential are then accumulated in the highconcentration region having a deep potential, which serves to suppressthe reduction of transfer efficiency. With this arrangement, thejunction capacitance (i.e., diffusion capacitance) of the diffusionregion 7 may be reduced, thereby improving the conversion efficiency ofan imaging device.

Further, the device isolation region 9 is likely to have crystal defects(or lattice defects) therein due to the characteristics of CMOSmanufacturing. Placing the device isolation region 9 in contact with thediffusion region, especially with the high concentration region 7 a, maymake it easier for dark current to flow, resulting in the degradation ofconversion efficiency.

In consideration of this, the low concentration regions 7 b arepreferably situated at such positions as to separate the highconcentration region 7 a from the device isolation region 9, i.e.,preferably situated between the high concentration region 7 a and thedevice isolation region 9 as illustrated in FIG. 3. The placement of thelow concentration regions 7 b at such positions enables the suppressionof dark current, thereby reducing a decrease in conversion efficiency.

In the plan view shown in FIG. 3, the low concentration regions 7 b areplaced in contact with, and on both sides of, the high concentrationregion 7 a. Such an arrangement of the low concentration regions 7 bwith respect to the high concentration region 7 a enables the lowconcentration regions 7 b to be situated in the proximity of the contactpoint of the diffusion region 7 that is in contact with the transfertransistor (i.e., the point where dark current is likely to flow).Accordingly, the occurrence of dark current is suppressed while reducingthe diffusion capacitance of the diffusion region 7, which may reliablyimprove conversion efficiency.

Further, since the point of the diffusion region 7 in contact with thetransistor 5 is constituted by the high concentration region 7 a and thelow concentration regions 7 b, the source of the diffusion region 7 maybe made to have a large area. As a result, the transfer characteristicsof electric charge may also be improved.

The impurity concentration of the low concentration regions 7 b of thediffusion region 7 is lower than in a low concentration region having atypical LDD (lightly doped drain) structure. Further, the lowconcentration regions 7 b have a larger area size than alow-impurity-concentration region that may be naturally formed in theproximity of a junction when a typical PN junction is formed.

Part of the high concentration region 7 a of the diffusion region 7, asconnected to the transistor 5, constitutes a contact area that is partof the transistor 5. In other words, this part of the transistor 5doubles as part of the high concentration region 7 a of the diffusionregion 7.

The high concentration region 7 a is substantially unnecessary in areasother than the contact area. In the case of manufacturing by use of atypical CMOS process, a process of doping impurity by use of a resistmask creates the high concentration region 7 a. The area size of thehigh concentration region 7 a is thus made substantially larger than thecontact area size of the contact area. On the other hand, an increase inthe area size of the diffusion region 7 may increase the diffusioncapacitance (i.e., junction capacitance) at the floating diffusion,thereby causing reduction in conversion efficiency.

In the present example, the diffusion region 7 and the transistor 5share the n-type high concentration region 7 a, such that the highconcentration region 7 a also serves as the contact area of thetransistor 5 at which the diffusion region 7 is coupled to the channelunder the gate 51 of the transistor 5 (i.e., the region where electriccharge is likely to be accumulated in effect), as illustrated in FIG. 3.The distribution of impurity concentration is set such that theremaining area of the diffusion region 7 serves as the n-type lowconcentration regions 7 b.

Compared with the high concentration region 7 a, the junctioncapacitance of the low concentration regions 7 b is extremely low.Because of this, the junction capacitance of the diffusion region 7 as awhole is made small, resulting in improvements in conversion efficiency.Further, electric charge transferred from the photodiode 3 to the lowconcentration regions 7 b having a shallow potential in the diffusionregion 7 is then collected in the high concentration region 7 a having adeep potential, which serves to maintain transfer efficiency.

FIG. 4 is a drawing illustrating an example of the pixel unitconstituting an imaging device according to a third embodiment. In thepixel 1 illustrated in FIG. 4, a portion of the semiconductor substrateSub forms the low concentration regions 7 b. The area size of thisportion of the semiconductor substrate Sub is substantially equal to thearea size of the low concentration area (N−) illustrated in FIG. 1.

The semiconductor substrate Sub has an impurity concentration that issubstantially lower than the impurity concentration of a highconcentration area. The use of portions of the semiconductor substrateSub to form the low concentration regions 7 b of the diffusion region 7serves to reduce the diffusion capacitance of the diffusion region 7.Accordingly, the junction capacitance of the diffusion region 7 as awhole is made small, resulting in improvements in conversion efficiency.

Moreover, the use of portions of the semiconductor substrate Sub as thelow concentration regions 7 b eliminates the need to use another memberfor forming a low concentration region at the floating diffusion. Inother words, a conventional CMOS manufacturing process (such as etching,etc.) may be used to form the low concentration regions, therebyreducing manufacturing costs.

FIG. 5 is a drawing illustrating an example of the pixel unitconstituting an imaging device according to a fourth embodiment. Thepixel 1 in FIG. 5 includes a transistor 11. The transistor 11 iselectrically coupled to the diffusion region 7. The transistor 11 servesto reset (thereby making a voltage change to) the potential of electriccharge accumulated in the diffusion region 7 to a reset potential.

The transistor 11 has a reset gate 11 a constituting the contact partthat is in contact with the diffusion region 7. The reset gate 11 a isdisposed such that the diffusion region 7 is placed between the resetgate 11 a and the gate 51 of the transistor 5. The transistor 11 is anexample of the reset transistor.

The provision of the transistor 11 allows the diffusion region 7 toserve as the source of the transistor 11. The diffusion region 7 alsoserves as the drain of the transistor 5. As a result, the source of thetransistor 11 and the drain of the transistor 5 are consolidated at theFD region. This arrangement serves to reduce the diffusion capacitanceof the diffusion region 7. Accordingly, the junction capacitance of thediffusion region 7 as a whole is made small, resulting in improvementsin conversion efficiency.

FIG. 6 is a drawing illustrating an example of the pixel unitconstituting an imaging device according to a fifth embodiment. Thepixel 1 in FIG. 6 further includes a transistor 13.

The transistor 13 amplifies a signal voltage made through the transferand conversion of electric charge at the diffusion region 7. Thetransistor 13 is an example of the amplifier transistor.

The transistor 13 includes an amplifier gate 13 a and drain/sourcediffusion regions 13 b. The amplifier gate 13 a brings about a gatecapacitance component among the entire capacitance of the diffusionregion 7. The amplifier gate 13 a is coupled to the high concentrationregion 7 a of the diffusion region 7 through a metal interconnect 15. Adiffusion region lib of the transistor 11 is also illustrated to which areset voltage is applied.

The provision of the transistor 13 serves to further improve thetransfer characteristics of the pixel and to reduce the capacitance ofthe diffusion region, thereby improving conversion efficiency. Moreover,the provision of such a transistor 13 allows the amplified electricsignal to be sent to the outside, thereby allowing a plurality of pixelsto be easily combined into an imaging device.

FIG. 7 is a drawing illustrating an example of the pixel unitconstituting an imaging device according to a sixth embodiment. In thepixel 1 illustrated in FIG. 7, the transistor 5 has a portion thereofextending toward the diffusion region 7 as an extension part 54 incomparison with the configuration in FIG. 1. As illustrated in FIG. 7,the extension part 54 is an edge of the transistor 5 situated toward thediffusion region 7 and projecting toward the diffusion region 7, therebyoverlapping part of the diffusion region 7. The provision of theextension part 54 serves to reduce the size of the diffusion region 7.

Namely, the extension part 54 constitutes the area (i.e., contact area)at which a portion of the diffusion region 7 is in contact with thetransistor 5, and the part of the transistor 5 becomes the part of thediffusion region 7, which serves to reduce the area size of thediffusion region 7.

FIG. 8 is a drawing illustrating an example of the pixel unit in whichthe pixels of the fifth embodiment illustrated in FIG. 6 are arranged. Apixel unit 14 illustrated in FIG. 8 has a plurality of pixels 1, amongwhich the pixels 1 a and 1 b are aligned in line in the verticaldirection (top-and-bottom direction) in the plan view to form a pixelgroup 17. Pixel groups 17 are then arranged side by side in thehorizontal direction (left-and-right direction) in the plan view of FIG.8.

Each of the pixels 1 a and 1 b constituting the same pixel group 17 iscoupled to the same vertical signal line 19 through a metal interconnect21. The vertical signal line 19 serves to transmit an electrical signalproduced by each pixel 1 to a read-out signal processing unit (i.e., aread-out signal processing unit 27 illustrated in FIG. 9, which will bedescribed later).

The pixel group 17 is an example of the pixel unit line. The verticaldirection is an example of the first direction, and the horizontaldirection is an example of the second direction perpendicular to thefirst direction. The vertical signal line 19 is an example of the signalline.

The alignment direction of pixels constituting the pixel group 17 andthe direction in which the pixel groups 17 are arranged side by side arenot limited to particular directions. Nonetheless, the pixel groups 17each of which is made by aligning the pixels 1 in the vertical directionmay be arranged side by side in the horizontal direction, therebyallowing a plurality of pixels to be arranged at high density in thepixel unit 14. Further, this arrangement also allows the length of eachvertical signal line to be made short. As a result, a high-resolutionsolid-state imaging device is provided for which transfercharacteristics are improved, and for which both sufficient light inputand sufficient saturation are secured.

Although not illustrated, each pixel of the pixel group 17 mayalternatively be coupled to a different vertical signal line 19 in thepixel unit 14. For example, two pixels may constitute the pixel group17, for which two vertical signal lines are used. One of the two pixelsis coupled to one of the two vertical signal lines through a metalinterconnect, and the other one of the two pixels is coupled to theother one of the two vertical signal lines through another metalinterconnect.

Such couplings between the pixels and the vertical signal lines allowsignals to be read from the pixels simultaneously. This arrangementenables the high-speed operation of an imaging device and theimprovement of transfer characteristics.

In the following, a description will be given of an example of theoperation of the imaging device (i.e., solid-state imaging device)according to the present disclosures. FIG. 9 is a drawing illustratingan example of the schematic configuration of the imaging device (i.e.,solid-state imaging device) of the present disclosures. A solid-stateimaging device 23 of this example includes a control circuit 25, a pixelunit 14, and a read-out signal processing unit 27.

The control circuit 25, which is coupled to the pixel unit 14, transmitsto the pixel unit 14 drive signals for driving the pixel unit 14.

The pixel unit 14 has a plurality of pixels 1 arranged therein, andserves as an example of the pixel unit used in the imaging device of thepresent disclosures. The pixel unit 14 is coupled to the read-out signalprocessing unit 27 via the vertical signal lines 19 to which each pixel1 is coupled. The pixel unit 14 operates in response to the drivesignals from the control circuit 25 so as to transmit the output signalof each pixel 1 to the read-out signal processing unit 27.

The read-out signal processing unit 27 includes read-out circuits 29 forreading the output signals of the pixels 1 and a data transfer unit 31for transmitting the output signals read by the read-out circuits 29 tothe outside as signal data.

The read-out circuits 29 may be an analog amplifier when the outputsignals are read as analog signals, and may be an AD conversion circuitwhen the output signals are read as digital signals. In this example,the read-out circuits 29 illustrated in FIG. 9 are AD conversioncircuits.

The data transfer unit 31 may be an analog-output amplifier when thesignals processed by the read-out signal processing unit 27 are analogsignals. In the case of digital signals digitized by the AD conversioncircuits or the like, a differential amplifier circuit for digital datamay instead be used. In this example, a differential amplifier circuitis used as the data transfer unit 31.

FIG. 10 is a drawing illustrating the circuit configuration of the pixel1 used in the pixel unit 14 of the imaging device illustrated in FIG. 9.The pixel 1 includes a photodiode PD, a transfer transistor TX, resettransistor RT, an amplifier transistor SF, and a floating diffusion FD.

The pixel 1 further includes a power supply line VDD, atransfer-transistor controlling line (transfer controlling line) LTX, areset-transistor controlling line (reset controlling line) LRT, and apower-supply controlling line LVDDRT for the reset transistor RT.

The transfer transistor TX provides a coupling between the photodiode PDand the floating diffusion FD serving as an output node. The transfertransistor TX receives a drive signal from the control circuit 25through the transfer controlling line LTX to transfer the electriccharge (or electrons) obtained through photoelectric conversion by thephotodiode PD to the floating diffusion FD.

The reset transistor RT provides a coupling between the resetpower-supply controlling line LVDDRT and the floating diffusion FD. Thereset transistor RT has a gate thereof receiving a reset-purpose drivesignal from the control circuit 25 through the reset controlling lineLRT. With this arrangement, the electric potential of the floatingdiffusion FD is reset by the electric potential of the reset powersupply LVDDRT.

The floating diffusion FD, which provides a coupling between thetransfer transistor TX and the reset transistor RT, is coupled to thegate of the amplifier transistor SF.

The amplifier transistor SF is coupled to the vertical signal line 19,thereby constituting a source follower with a constant current sourceprovided outside the pixel unit 14. The amplifier transistor SFamplifies the electric potential of the floating diffusion FD to outputa voltage responsive to the potential to the vertical signal line 19.The voltage output from the pixel 1 is supplied to the read-out signalprocessing unit 27 through the vertical signal line 19.

The reset controlling line LRT, the transfer controlling line LTX, andthe reset power-supply controlling line LVDDRT placed in the pixel unit14 together form a set, and a set of these lines is provided for eachrow on which a plurality of pixels are arranged as illustrated in FIG.9. The reset controlling line LRT, the transfer controlling line LTX,and the reset power-supply controlling line LVDDRT are driven by thecontrol circuit 25.

In the following, a description will be given of the operation timing ofa pixel used in the pixel unit of the imaging device of the presentdisclosures, with reference to FIG. 11. Waveforms illustrated in FIG. 11represent the operations of the respective lines or nodes illustrated inFIG. 10. Each waveform illustrates an operation in a timeframe inclusiveof the period between a read time t_(dark) for reading a reset signal ofthe pixel 1 and a read time t_(sig) for reading a signal level of thepixel 1.

The reset power-supply controlling line LVDDRT provides a power supplyvoltage VDD. This arrangement enables the reading of a pixel in thepixel unit 14. Subsequently, a test signal inputting gate TFD (notshown) is coupled to the ground. As a result, an amplifier transistorTSF in the test output signal unit (not shown) is disconnected from thevertical signal line, followed by reading the output signal of eachpixel 1 of the pixel unit 14.

The operation of reading the output signal of the pixel 1 as describedin a time sequence will be as follows. The reset controlling line LRTcoupled to the gate of the reset transistor RT is set to the high-levelvoltage VDD before the read time t_(dark) for reading a reset signal.The floating diffusion FD is thus reset to the reset potentialVFD_(dark).

At the read time t_(dark) for reading a reset signal, the read-outsignal processing unit 27 receives the output signal supplied from theamplifier transistor SF to the vertical signal line 19, thereby readingthe potential level VFD_(dark) of the floating diffusion FD reset by thereset voltage.

Subsequently, the transfer controlling line LTX supplies the high-levelvoltage VDD to the transfer transistor TX before the read time t_(sig)for reading a signal level, thereby transferring the electrons (i.e.,electric charge) accumulated in the photodiode PD to the floatingdiffusion FD (i.e., performs electric charge transfer).

At the read time t_(sig) for reading a signal level, the read-out signalprocessing unit 27 receives the output signal supplied from theamplifier transistor SF to the vertical signal line 19, thereby readingthe voltage VFD_(sig) having a signal level responsive to the FDcapacitance and the number of electrons transferred by the electriccharge transfer.

FIG. 12 is a drawing illustrating an example of a camera system to whichthe imaging device of the present disclosures is applied. A camerasystem 33 illustrated in FIG. 12 includes a solid-state imaging device23, a lens 35, a drive circuit 37, and a signal processing circuit 39.The solid-state imaging device 23 may be the imaging device illustratedin FIG. 8 and FIG. 9.

The lens 35, which constitutes a camera lens optical system, forms animage of incident light on the imaging surface of the pixel area of thesolid-state imaging device 23. The drive circuit 37, which serves as adrive unit of the camera system, drives the solid-state imaging device23. The signal processing circuit 39, which serves as a signalprocessing unit of the camera system, performs predetermined signalprocessing with respect to output signals supplied from the solid-stateimaging device 23.

Image signals processed by the signal processing circuit 39 are storedin a recording medium such as a memory through an analog-digitalconversion circuit (AFE) in the case of the image signals being analogoutputs, or through a digital signal processing (DFE) in the case of theimage signals being digital outputs. Image information stored in therecording medium may be supplied to a printer to produce a hard copy.The image signals processed by the signal processing unit may besupplied to a monitor such as a liquid display to be displayed as videoimages.

As described heretofore, the provision of the above-describedsolid-state imaging device in an imaging apparatus brings about theadvantages as described (e.g., improvements in transfer characteristicswhile securing sufficient input light entering the photoelectricconversion element), thereby providing a high-precision camera as animaging apparatus.

According to at least one embodiment, the transfer characteristics of animaging device are improved while securing sufficient light input.

Although the embodiments of the present invention have been described,the present invention is not limited to these embodiments, but variousvariations and modifications may be made without departing from thescope of the present invention.

RELATED-ART DOCUMENTS Patent Document

[Patent Document 1] Japanese Unexamined Patent Application PublicationNo. 2003-258231

What is claimed is:
 1. A pixel unit, comprising: a photoelectricconversion element; a transfer gate abutting on the photoelectricconversion element and having a portion thereof surrounded by thephotoelectric conversion element in a plan view; and a floatingdiffusion region abutting on another portion of the transfer gate whichis not surrounded by the photoelectric conversion element in the planview, wherein the portion of the transfer gate surrounded by thephotoelectric conversion element is configured not to broaden away fromthe floating diffusion region and to have a region thereof situated awayfrom the floating diffusion region that gradually narrows away from thefloating diffusion region.
 2. The pixel unit according to claim 1,wherein the region of the transfer gate situated away from the floatingdiffusion region is tapered.
 3. The pixel unit according to claim 1,wherein the transfer gate has a plan shape made by cutting off twocorners of a rectangle among four corners thereof, the two corners beingsituated away from the floating diffusion region.
 4. The pixel unitaccording to claim 1, wherein the photoelectric conversion element, thetransfer gate, and the floating diffusion region are aligned in line. 5.The pixel unit according to claim 1 wherein the floating diffusionregion includes a first diffusion region and second diffusion regions,the first diffusion region having an impurity concentration differentthan the second diffusion regions, and wherein the first diffusionregion has a higher impurity concentration than the second diffusionregions, and the first diffusion region is situated in contact with andbetween the second diffusion regions.
 6. The pixel unit according toclaim 1, further comprising a reset transistor coupled to the floatingdiffusion region and configured to reset electric charge accumulated inthe floating diffusion region.
 7. The pixel unit according to claim 1,further comprising an amplifier transistor coupled to the floatingdiffusion region and configured to amplify a voltage of the floatingdiffusion region.
 8. The pixel unit according to claim 1, wherein thetransfer gate further includes an extension part projecting over thefloating diffusion region.
 9. An imaging device comprising a pluralityof pixel units each having a configuration of the pixel unit of claim 1,wherein some of the pixel units are aligned in a first direction, toform any given one of a plurality of pixel unit lines, and the pluralityof pixel unit lines are arranged side by side in a second directionperpendicular to the first direction.
 10. The imaging device accordingto claim 9, wherein some of the pixel units that form one of theplurality of pixel unit lines are coupled to a same signal lineconfigured to read electric signals from said some of the pixel units.